Image display system

ABSTRACT

Image display systems comprising a first pixel, a second pixel, a scan line, a first data line, and a second data line. In the first pixel, a first transistor is coupled to a first storage capacitor via a first pixel electrode. In the second pixel, a second transistor is coupled to a second storage capacitor via a second pixel electrode. The conductance of the first and second transistors is simultaneously controlled by a scan signal transmitted by the scan line. In a first time interval, the first data line transmits a voltage data to the first pixel electrode via the first transistor. In a second time interval, the second data line transmits the voltage data to the second pixel electrode via the second transistor. The first storage capacitor is designed to generate a proper feedthrough voltage at the first pixel electrode to compensate for a voltage coupling shift at the first pixel electrode that is generated during the second time interval because of the voltage variation at the second pixel electrode.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to image display systems, andparticularly, to image display systems that reduce the color shift ofconventional image display systems.

2. Description of the Related Art

FIG. 1 shows a portion of a conventional display panel. The displaypanel 100 comprises a red pixel R, a green pixel G, and a blue pixel B.The pixels each comprise a transistor T and a storage capacitor C_(st).The gates of the transistors T are coupled to a scan line (Scan). Thescan line (Scan) transports a scan signal to control the conductance ofthe transistors T. The drains of the transistors T of the pixels R, Gand B are coupled to data lines D_(r), D_(g) and D_(b), respectively.

To reduce the total number of pins of a display panel chip, the displaypanel 100 comprises a demultiplexer 102 and the pixels R, G and B sharea single voltage data source (Data). The demultiplexer 102 comprisesthree switches SW_(r), SW_(g), and SW_(b) that are controlled by pulsesignals CKH_(r), CKH_(g) and CKH_(b), respectively. FIG. 2 shows thedriving signals of the display panel 100 (Scan, CKH_(r), CKH_(g) andCKH_(b)) and the voltage levels of the pixel electrodes of the pixels R,G and B (V_(r), V_(g) and V_(b)), wherein a row inversion technique isapplied to the display panel 100. When the scan signal transported bythe scan line (Scan) is high, the conductance of the transistors T ofthe pixels R, G and B are high and the voltage data source (Data) sendsout voltage data to the pixels R, G and B. Referring to FIG. 2, at timeindex t₁, the pulse signal CKH_(r) turns on the switch SW_(r) and thevoltage data sent from Data is transported to the red pixel R (whereinV_(r) is set to the voltage data), at time index t₂, the pulse signalCKH_(g) turns on the switch SW_(g) and the voltage data sent from Datais transported to the green pixel G (wherein V_(g) is set to the voltagedata) and, at time index t₃, the pulse signal CKH_(b) turns on theswitch SW_(b) and the voltage data sent from Data is transported to theblue pixel B (wherein V_(b) is set to the voltage data). Because of avoltage coupling effect at the pixel electrodes of the pixels R, G andB, V_(r), V_(g) and V_(b) mutually affect one another. As shown in FIG.2, at time index t₂, the voltage level of the red pixel electrode(V_(r)) is shifted by the voltage variation at the green pixelelectrode, and symbol 202 marks the shift of V_(r). At time index t₃,the voltage level of the green pixel electrode (V_(g)) is shifted by thevoltage variation at the blue pixel, and symbol 204 marks the shift ofV_(g). The variation of V_(g) (marked by 204) further causes a voltageshift at the red pixel (marked by symbol 206). In this case, the redpixel has the greatest voltage coupling shift because the voltage levelof the red pixel electrode (V_(r)) not only varying with the voltagevariation at the green pixel electrode but also varying with the voltagevariation at the blue pixel electrode.

As shown in FIG. 2, the voltage data source (Data) provides the samevoltage data to the pixels R, G and B. In a case where a normally whitetechnique is adopted such that the liquid crystal material is previousto light when the voltage data applied to it is zero and the luminousintensity of a pixel decreases when the voltage difference between thepixel electrode and the common electrode increases, the red pixel hasthe lowest luminous intensity and the blue pixel has the greatestluminous intensity. Images displayed by the display panel 100 are biasedby a blue color shift. In another case where a normally black techniqueis adopted such that the liquid crystal material is opaque when thevoltage data applied to it is zero and the luminous intensity of a pixelincreases with increasing voltage difference between the pixel electrodeand the common electrode, the red pixel has the greatest luminousintensity and the blue pixel has the lowest luminance intensity. Imagesdisplayed by the display panel 100 are biased by a red color shift.

BRIEF SUMMARY OF THE INVENTION

The invention provides image display systems to deal with the colorshift problem of the conventional display panel 100.

In the convention display panel 100, the capacitance of storagecapacitors of all pixels are the same. In the invention, each storagecapacitor is exclusively designed. The capacitance of the storagecapacitors are designed according to the voltage coupling shifts at thepixel electrodes that are caused by voltage coupling effect.

Referring to FIG. 2, the scan line (Scan) drops from high to low at timeindex t₄ to switch the transistors T of the pixels to high impedance. Attime index t₄, the voltage level of the scan line (Scan) is shifted byΔV_(gate). The voltage variation at the scan line (Scan) causes afeedthrough voltage effect at the red, green and blue pixels. Thevoltage levels of the red, green and blue pixels (V_(r), V_(g) andV_(b)) are shifted by feedthrough voltages V_(fr), V_(fg) and V_(fb),respectively. The value of the feedthrough voltages V_(fr), V_(fg) andV_(fb) are dependent on the capacitance of the storage capacitors of thepixels. The invention specifically designs the storage capacitors of thepixels to generate proper feedthrough voltages V_(fr), V_(fg) and V_(fb)to compensate for the voltage coupling shifts at the pixel electrodes.

The above and other advantages will become more apparent with referenceto the following descriptions taken in conjunction with the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the subsequentdetailed description and examples with references made to theaccompanying drawings, wherein:

FIG. 1 shows a portion of a conventional display panel;

FIG. 2 shows the waveforms of the driving signals (Scan, CKH_(r),CKH_(g) and CKH_(b)) and the voltage levels of the pixel electrodes(V_(r), V_(g) and V_(b));

FIG. 3 shows a portion of a display panel of an embodiment of theinvention;

FIG. 4 shows the waveforms of the driving signals (Scan, CKH_(r),CKH_(g) and CKH_(b)) and the voltage levels of the pixel electrodes(V_(r), V_(g) and V_(b));

FIG. 5 shows a portion of a display panel of another embodiment of theinvention;

FIG. 6 shows the waveforms of the driving signals (Scan, CKH_(r),CKH_(g) and CKH_(b)) and the voltage levels of the pixel electrodes(V_(r), V_(g) and V_(b));

FIG. 7 illustrates an embodiment of the invention;

FIG. 8 illustrates another embodiment of the invention; and

FIG. 9 shows an electronic device.

DETAILED DESCRIPTION OF THE INVENTION

The following description is made for the purpose of illustrating thegeneral principles of the invention and should not be taken in alimiting sense. The scope of the invention is best determined byreference to the appended claims.

FIG. 3 shows a portion of a display panel of an embodiment of theinvention. The display panel 300 comprises a red pixel R, a green pixelG, and a blue pixel B. The red pixel R comprises a transistor T and astorage capacitor C_(str), wherein the transistor T is coupled to thestorage capacitor C_(str) via a red pixel electrode. The voltage levelof the red pixel electrode is V_(r). The green pixel G comprises atransistor T and a storage capacitor C_(stg), wherein the transistor Tis coupled to the storage capacitor C_(stg) via a green pixel electrode.The voltage level of the green pixel electrode is V_(g). The blue pixelB comprises a transistor T and a storage capacitor C_(stb), wherein thetransistor T is coupled to the storage capacitor C_(stb) via a bluepixel electrode. The voltage level of the blue pixel electrode is V_(b).The gates of the transistors T of the pixels R, G and B are coupled to ascan line (Scan). The scan line (Scan) transports a scan signal tocontrol the conductance of the transistors T. The drains of thetransistors T of the pixels R, G and B are coupled to data lines D_(r),D_(g) and D_(b), respectively. To reduce the pins of the display panelchip, the display panel 300 comprises a demultiplexer 102 similar tothat of the conventional display panel 100. The pixels R, G and B,therefore, share a single voltage data source (Data). The demultiplexer102 comprises three switches SW_(r), SW_(g) and SW_(b) that arerespectively controlled by pulse signals CKH_(r), CKH_(g) and CKH_(b).

Comparing the display panel 300 with the conventional display panel 100,all pixels of the conventional display panel 100 have the same storagecapacitors C_(st), and the pixels of the display panel 300 haveexclusively designed storage capacitors. For example, C_(str), C_(stg)and C_(stb) are specifically designed for the different pixels R, G andB. FIG. 4 shows the waveforms of the driving signals of the displaypanel 300 (Scan, CKH_(r), CKH_(g), and CKH_(b)) and the voltage levelsof the pixel electrodes (V_(r), V_(g), and V_(b)), wherein the displaypanel has specially designed storage capacitors C_(str), C_(stg) andC_(stb). Referring to waveforms Scan, CKH_(r), CKH_(g), and CKH_(b), thered pixel R is activated prior to the green pixel G and the green pixelis activated prior to the blue pixel B. The voltage data sent from thevoltage data source (Data) is transported to the pixels R, G and B attime indexes t₁, t₂ and t₃, respectively. In an embodiment of theinvention, the pixels R, G and B are in the same gamma setting and aredriven by the same gray level, the voltage level at which V_(r) islocked during time indexes t₁˜t₂ equals to the voltage level at whichV_(g) is locked during time indexes t₂˜t₃ and equals to the voltagelevel at which V_(b) is locked during time indexes t₃˜t₄. Because of thevoltage coupling effect, V_(r) is shifted by voltage variations at thegreen and blue pixel electrodes (the variations at V_(g) and V_(b)) andV_(g) is shifted by the voltage variation at the blue pixel electrode(the variation at V_(b)). At the red pixel electrode, the voltagecoupling shift caused by the voltage coupling effect is ΔV_(r). At thegreen pixel electrode, the voltage coupling shift caused by the voltagecoupling effect is ΔV_(g).

Compared to FIG. 3, FIG. 5 further shows liquid crystal capacitorsC_(lc) and parasitic capacitors C_(gd) of the transistors T. When thescan line (Scan) changes from high to low, V_(r), V_(g) and V_(b) varywith the voltage variation at the scan line (ΔVgate), wherein thevoltage drop in V_(r), V_(g) and V_(b) are named feedthrough voltages.Referring to FIG. 4, at time index t₄, the feedthrough voltages atpixels R, G and B are symbolized as V_(fr), V_(fg) and V_(fb),respectively. Based on the circuit shown in FIG. 5, the value of thefeedthrough voltages V_(fr), V_(fg) and V_(fb) are:

$\begin{matrix}{{V_{fr} = {\Delta \; V_{gate} \times \frac{C_{gd}}{C_{str} + C_{lc} + C_{gd}}}},} & \left( {{eq}.\mspace{11mu} 1} \right) \\{{V_{fg} = {\Delta \; V_{gate} \times \frac{C_{gd}}{C_{std} + C_{lc} + C_{gd}}}},} & \left( {{eq}.\mspace{11mu} 2} \right) \\{V_{fb} = {\Delta \; V_{gate} \times {\frac{C_{gd}}{C_{stb} + C_{lc} + C_{gd}}.}}} & \left( {{eq}.\mspace{11mu} 3} \right)\end{matrix}$

To compensate for the voltage coupling shifts ΔV_(r) and ΔV_(g) thatcause color shift, the invention specifically designs the capacitance ofthe storage capacitors C_(str), C_(stg) and C_(stb) to generate properfeedthrough voltages V_(fr), V_(fg) and V_(fb).

Referring to FIG. 4, to reduce color shift of the display panel, thefeedthrough voltages V_(fr), V_(fg) and V_(fb) have to satisfy thefollowing equation:

ΔV+ΔV _(r) −V _(fr) =ΔV+ΔV _(g) −V _(fg) =ΔV−V _(fb).

Therefore, V_(fr)=ΔV_(r)+V_(fb) and V_(fg)=ΔV_(g)+V_(fb). In anembodiment of the invention, capacitance of C_(stb) is already known andthe voltage coupling shifts ΔV_(r) and ΔV_(g) have been calculated by acomputer simulation program, adopting (eq. 1) and (eq. 2), thecapacitance of the storage capacitors C_(str) and C_(stg) are designedaccording to the following formulas:

${C_{str} = {\frac{\Delta \; V_{gate} \times C_{gd}}{{\Delta \; V_{r}} + V_{fb}} - C_{lc} - C_{gd}}},{and}$$C_{stg} = {\frac{\Delta \; V_{gate} \times C_{gd}}{{\Delta \; V_{g}} + V_{fb}} - C_{lc} - {C_{gd}.}}$

where V_(fb) follows (eq.3).

In another embodiment of the invention, the pixels R, G and B are drivenin a sequence different from that of the embodiment shown in FIG. 4, thedesign rule of the storage capacitors C_(str), C_(stg) and C_(stb)require modification accordingly.

In the embodiment shown in FIG. 6, the blue pixel B is driven beforedriving the green pixel G, and the green pixel G is driven beforedriving the red pixel R. The voltage data source (Data) transports avoltage data to the pixels B, G and R at time indexes t₁, t₂ and t₃,respectively. To reduce the color shift of the display panel, thefeedthrough voltages V_(fr), V_(fg) and V_(fb) have to satisfy thefollowing equation:

ΔV+ΔV _(b) −V _(fb) =ΔV+ΔV _(g) −V _(fg) =ΔV−V _(fr).

Therefore, V_(fb)=ΔV_(r)+V_(fr) and V_(fg)=ΔV_(g)+V_(fr). In anembodiment of the invention, the capacitance of C_(str) is already knownand the voltage coupling shifts ΔV_(b) and ΔV_(g) have been calculatedby a computer simulation program, while (eq. 2) and (eq. 3) are adopted,the capacitance of the storage capacitors C_(stb) and C_(stg) aredesigned according to the following formulas:

${C_{stb} = {\frac{\Delta \; V_{gate} \times C_{gd}}{{\Delta \; V_{b}} + V_{fr}} - C_{lc} - C_{gd}}},{and}$${C_{stg} = {\frac{\Delta \; V_{gate} \times C_{gd}}{{\Delta \; V_{g}} + V_{fr}} - C_{lc} - C_{gd}}},$

where V_(fr) follows (eq. 1).

The embodiments shown in FIGS. 4 and 6 reveal that the technique of theinvention can be applied to any display panel comprising pixels sharinga single scan line and activated in different time indexes.

FIG. 7 shows an embodiment of the invention. As shown in FIG. 7, animage display system comprises a first pixel P₁, a second pixel P₂, ascan line (Scan), a first data line D₁, and a second data line D₂. Thefirst pixel P₁ comprises a first transistor T₁ and a first storagecapacitor C_(st1). The first storage capacitor C_(st1) is coupled to thesource of the first transistor T₁ via a first pixel electrode. Thevoltage level of the first pixel electrode is V₁. The second pixel P₂comprises a second transistor T₂ and a second storage capacitor C_(st2).The second storage capacitor C_(st2) is coupled to the source of thesecond transistor T₂ via a second pixel electrode. The voltage level ofthe second pixel electrode is V₂. The gates of the first and secondtransistors T₁ and T₂ are coupled to the scan line (Scan). The scan line(Scan) transports a scan signal to control the conductance of the firstand second transistors T₁ and T₂. The drains of the first and secondtransistors T₁ and T₂ are coupled to the first and second data lines D₁and D₂, respectively. The demultiplexer 702 routes the voltage data sentout from the voltage data source (Data) to the first data line D₁ or thesecond data line D₂. Under the control of the control signal CS, thevoltage data is sent to the first data line D₁ during a first timeinterval and is sent to the second data line D₂ during a second timeinterval. The first time interval is prior to the second time interval.

Because of the voltage coupling effect, when the voltage data is writtento the second pixel electrode during the second time interval, thevoltage level at the first pixel electrode (V₁) is shifted, too. Thevoltage variation at the first pixel electrode caused by the voltagecoupling effect is named voltage coupling shift. At the time point thatthe first and second transistors T₁ and T₂ are switched to a highconductance state by the scan line (Scan), the voltage variation at thescan line (Scan) causes feedthrough voltage effects at the pixelelectrodes. The voltage level of the first pixel electrode (V₁) isshifted by a first feedthrough voltage. Because the value of the firstfeedthrough voltage is dependent on the capacitance of the first storagecapacitance C_(st1), the invention designs the first storage capacitorC_(st1) to generate a proper first feedthrough voltage to compensate forthe voltage coupling shift at the first pixel electrode.

Furthermore, the voltage level at the second pixel electrode (V₂) isshifted by a second feedthrough voltage. In an embodiment of theinvention, the capacitance of the first storage capacitor C_(st1) isdesigned to make the first feedthrough voltage equal to the sum of thesecond feedthrough voltage and the voltage coupling shift at the firstpixel electrode. In an embodiment of the invention, the capacitance ofthe first storage capacitor C_(st1) follows the following formula:

${C_{{st}\; 1} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 1}}{{\Delta \; V_{1}} + V_{f\; 2}} - C_{{lc}\; 1} - C_{{gd}\; 1}}},$

where C_(gd1) represents the capacitance of the parasitical capacitorcoupled between the gate and drain of the first transistor T₁, C_(lc1)represents the capacitance of the liquid crystal capacitor of the firstpixel P₁, and ΔV_(gate) represents the voltage variation at the scanline (Scan). ΔV₁ represents the voltage coupling shift at the firstpixel electrode, and is calculated by a computer simulation program.V_(f2) represents the second feedthrough voltage. The value of V_(f2) iscalculated according to the following formula:

$V_{f\; 2} = {\Delta \; V_{gate} \times \frac{C_{{gd}\; 2}}{C_{{st}\; 2} + C_{{lc}\; 2} + C_{{gd}\; 2}}}$

where C_(st2) represents the capacitance of the second storagecapacitor, C_(gd2) represents the capacitance of the parasiticalcapacitor coupled between the gate and drain of the second transistorT₂, and C_(lc2) represents the capacitance of the liquid crystalcapacitor of the second pixel P₂.

In an embodiment of the invention where all pixels have the same liquidcrystal capacitor and the same parasitical capacitors, the capacitanceof the first storage capacitor C_(st1) is designed to be smaller thanthe capacitance of the second storage capacitor C_(st2).

Referring to FIG. 3, the above mentioned first and second pixels P₁ andP₂ are the green pixel G and the blue pixel B, respectively, when thered pixel R is driven prior to the green pixel G and the green pixel Gis driven prior to the blue pixel B. When the blue pixel B is drivenprior to the green pixel G and the green pixel G is driven prior to thered pixel R, the above mentioned first and second pixels P₁ and P₂ arethe green pixel G and the red pixel R, respectively.

FIG. 8 shows another embodiment of the invention. Compared to theembodiment shown in FIG. 7, the system further comprises a third pixelP₃ and a third data line D₃. The third pixel P₃ comprises a thirdtransistor T₃ and a third storage capacitor C_(st3). The third storagecapacitor C_(st3) is coupled to the third transistor T₃ via a thirdpixel electrode. The voltage level of the third pixel electrode is V₃.The drain of the third transistor T₃ is coupled to the third data lineD₃, and the gate of the third transistor T₃ is coupled to the scan line(Scan). Under the control of the control signal CS, the voltage datasent out from the voltage data source (Data) is coupled to the firstdata line D₁ during a first time interval, to the second data line D₂during a second time interval, and to the third data line D₃ during athird time interval. The first time interval is prior to the second timeinterval and the second time interval is prior to the third timeinterval. In this case, in addition to designing the capacitance of thefirst storage capacitor C_(st1), the invention designs the capacitanceof the second storage capacitor C_(st2). The first storage capacitorC_(st1) is designed to generate a proper feedthrough voltage at thefirst pixel electrode to compensate for the voltage coupling shift atthe first pixel electrode, and the second storage capacitor C_(st2) isdesigned to generate a proper feedthrough voltage at the second pixelelectrode to compensate for the voltage coupling shift at the secondpixel electrode.

In addition to the feedthrough voltage effects at the first and secondpixel electrodes, the voltage variation at the scan line (Scan) alsocauses a feedthrough voltage effect at the third pixel electrode, whichshifts the voltage level of the third pixel electrode (V₃) by a thirdfeedthrough voltage. In an embodiment of the invention, the firststorage capacitor C_(st1) is designed to make the first feedthroughvoltage equal to the sum of the third feedthrough voltage and voltagecoupling shift at the first pixel electrode, and the second storagecapacitor C_(st2) is designed to make the second feedthrough voltageequal to the sum of the third feedthrough voltage and the voltagecoupling shift at the second pixel electrode.

In an embodiment of the invention, the first and second storagecapacitors C_(st1) and C_(st2) are designed according to the followingformulas:

${C_{{st}\; 1} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 1}}{{\Delta \; V_{1}} + V_{f\; 3}} - C_{{lc}\; 1} - C_{{gd}\; 1}}},{and}$${C_{{st}\; 2} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 2}}{{\Delta \; V_{2}} + V_{f\; 3}} - C_{{lc}\; 2} - C_{{gd}\; 2}}},$

where C_(gd1) represents the capacitance of the parasitic capacitorcoupled between the gate and drain of the first transistor T₁, C_(gd2)represents the capacitance of the parasitic capacitor coupled betweenthe gate and drain of the second transistor T₂, C_(lc1) and C_(lc2)respectively represent the capacitance of the liquid crystal capacitorsof the first and second pixels P₁ and P₂, and ΔV_(gate) represents thevoltage variation at the scan line (Scan). ΔV₁ and ΔV₂ represents thevoltage coupling shifts at the first and second pixel electrodes,respectively, and are calculated by a computer simulation program.V_(f3) represents the third feedthrough voltage and follows thefollowing formula:

${V_{f\; 3} = {\Delta \; V_{gate} \times \frac{C_{{gd}\; 3}}{C_{{st}\; 3} + C_{{lc}\; 3} + C_{{gd}\; 3}}}},$

where C_(st3) represents the capacitance of the third storage capacitor,C_(gd3) represents the capacitance of the parasitical capacitor coupledbetween the gate and drain of the third transistor T₃, and C_(lc3)represents the capacitance of the liquid crystal capacitor of the thirdpixel P₃.

In an embodiment of the invention, when the liquid crystal capacitors ofall pixels are the same and the parasitical capacitors are the same, thecapacitance of the first storage capacitor C_(st1) is designed to besmaller than the capacitance of the second storage capacitor C_(st2),and the capacitance of the second storage capacitor C_(st2) is designedto be smaller than the capacitance of the third storage capacitorC_(st3).

Referring to FIG. 3, the above mentioned first, second and third pixelsP₁, P₂ and P₃ are the red pixel R, the green pixel G and the blue pixelB, respectively, when the red pixel R is driven prior to the green pixelG and the green pixel G is driven prior to the blue pixel B. In anotherembodiment of the invention where the blue pixel B is driven prior tothe green pixel G and the green pixel G is driven prior to the red pixelR, the above mentioned first, second and third pixels P₁, P₂ and P₃ arethe blue pixel B, the green pixel G and the red pixel R, respectively.

FIG. 9 shows an electronic device 900 comprising a pixel array 902, adisplay panel 904, and an input unit 906. The input unit 906 receivesimage information and transmits the received image information to thedisplay panel 904.

The pixel array 902 comprises the pixels mentioned in the invention. Thedisplay panel 904 comprises the scan line and data lines mentioned inthe invention, The electronic device is a cell phone, a digital camera,a personal computer assistant, a notebook, a desktop, a television, acar display, or a portable DVD player.

While the invention has been described by way of example and in terms ofembodiments, it is to be understood that the invention is not limitedthereto. To the contrary, it is intended to cover various modificationsand similar arrangements (as would be apparent to those skilled in theArt). Therefore, the scope of the appended claims should be accorded tothe broadest interpretation so as to encompass all such modificationsand similar arrangements.

1. A image display system, comprising a first pixel, comprising a firsttransistor and a first storage capacitor, wherein the first storagecapacitor is coupled to the source of the first transistor via a firstpixel electrode; a second pixel, comprising a second transistor and asecond storage capacitor, wherein the second storage capacitor iscoupled to the source of the second transistor via a second pixelelectrode; a scan line, coupling the drains of the first and secondtransistors to transport a scan signal to control the conductance of thefirst and second transistors; a first data line, coupling the drain ofthe first transistor, and receiving a voltage data during a first timeinterval; and a second data signal, coupling the drain of the secondtransistor, and receiving the voltage data during a second time intervallater than the first time interval; wherein the first storage capacitoris designed to generate a first feedthrough voltage to compensate for avoltage coupling shift at the first pixel electrode, wherein the firstfeedthrough voltage is the voltage variation at the first pixelelectrode that varies with the scan signal.
 2. The system as claimed inclaim 1, wherein the voltage variation at the second pixel electrodethat varies with the scan signal is a second feedthrough voltage.
 3. Thesystem as claimed in claim 2, wherein the first storage capacitor isdesigned to make the value of the first feedthrough voltage equal to thesum of the second feedthrough voltage and the voltage coupling shift atthe first pixel electrode.
 4. The system as claimed in claim 3, whereinthe first storage capacitor is designed according to the followingformula:${C_{{st}\; 1} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 1}}{{\Delta \; V_{1}} + V_{f\; 2}} - C_{{lc}\; 1} - C_{{gd}\; 1}}},$where C_(st1) represents the capacitance of the first storage capacitor,C_(gd1) represents the capacitance of the parasitical capacitor coupledbetween the gate and drain of the first transistor, C_(lc1) representsthe capacitance of the liquid crystal capacitor of the first pixel,ΔV_(gate) represents the voltage variation at the scan signal, ΔV₁represents the voltage coupling shift at the first pixel electrode, andV_(f2) represents the second feedthrough voltage.
 5. The system asclaimed in claim 4, wherein the value of the second feedthrough voltageis calculated by the following formula:${V_{f\; 2} = {\Delta \; V_{gate} \times \frac{C_{{gd}\; 2}}{C_{{st}\; 2} + C_{{lc}\; 2} + C_{{gd}\; 2}}}},$where C_(st2) represents the capacitance of the second storagecapacitor, C_(gd2) represents the capacitance of the parasiticalcapacitor coupled between the gate and drain of the second transistor,and C_(lc2) represents the capacitance of the liquid crystal capacitorof the second pixel.
 6. The system as claimed in claim 4, wherein thevalue of the voltage coupling shift at the first pixel electrode iscalculated by a computer simulation program.
 7. The system as claimed inclaim 1, wherein the capacitance of the first storage capacitor issmaller than the capacitance of the second storage capacitor.
 8. Thesystem as claimed in claim 2, further comprising a third pixel, thethird pixel comprising a third transistor and a third storage capacitor,wherein the third storage capacitor is coupled to the source of thethird transistor via a third pixel electrode.
 9. The system as claimedin claim 8, wherein the scan line further couples the gate of the thirdtransistor.
 10. The system as claimed in claim 9, further comprising athird data line, wherein the third data line couples the drain of thethird transistor, and receives the voltage data during a third timeinterval later than the second time interval.
 11. The system as claimedin claim 10, wherein the second storage capacitor is designed to makethe second feedthrough voltage capable of compensating for a voltagecoupling shift at the second pixel electrode.
 12. The system as claimedin claim 11, wherein the voltage variation at the third pixel electrodethat varies with the scan signal is a third feedthrough voltage.
 13. Thesystem as claimed in claim 12, wherein the first storage capacitor isdesigned to make the value of the first feedthrough voltage equal to thesum of the third feedthrough voltage and the voltage coupling shift atthe first pixel electrode, and the second storage capacitor is designedto make the value of the second feedthrough voltage equal to the sum ofthe third feedthrough voltage and the voltage coupling shift at thesecond pixel electrode.
 14. The system as claimed in claim 13, whereinthe first and second storage capacitors are designed according to thefollowing formulas:${C_{{st}\; 1} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 1}}{{\Delta \; V_{1}} + V_{f\; 3}} - C_{{lc}\; 1} - C_{{gd}\; 1}}},{and}$${C_{{st}\; 2} = {\frac{\Delta \; V_{gate} \times C_{{gd}\; 2}}{{\Delta \; V_{2}} + V_{f\; 3}} - C_{{lc}\; 2} - C_{{gd}\; 2}}},$where C_(st1) and C_(st2) represent the capacitance of the first andsecond storage capacitors, respectively, C_(gd1) represents thecapacitance of the parasitical capacitor coupled between the gate anddrain of the first transistor, C_(gd2) represents the capacitance of theparasitical capacitor coupled between the gate and drain of the secondtransistor, C_(lc1) and C_(lc2) represent the capacitance of the liquidcrystal capacitors of the first and second pixels, respectively,ΔV_(gate) represents the voltage variation at the scan line, ΔV₁ and ΔV₂represent the voltage coupling shifts at the first and second pixelelectrodes, respectively, and V_(f3) represents the third feedthroughvoltage.
 15. The system as claimed in claim 14, wherein the value of thethird feedthrough voltage is calculated by the following formula:${V_{f\; 3} = {\Delta \; V_{gate} \times \frac{C_{{gd}\; 3}}{C_{{st}\; 3} + C_{{lc}\; 3} + C_{{gd}\; 3}}}},$where C_(st3) represents the capacitance of the third storage capacitor,C_(gd3) represents the capacitance of the parasitical capacitor coupledbetween the gate and drain of the third transistor, and C_(lc3)represents the capacitor of the liquid crystal capacitor of the thirdpixel.
 16. The system as claimed in claim 14, wherein the value of thevoltage coupling shifts at the first and second pixel electrodes arecalculated by a computer simulation program.
 17. The system as claimedin claim 11, wherein the capacitance of the first storage capacitor issmaller than the capacitance of the second storage capacitor, and thecapacitance of the second storage capacitor is smaller than thecapacitance of the third storage capacitor.
 18. The system as claimed inclaim 1, further comprising a display panel that comprises the firstpixel, the second pixel, the scan line, the first data line, and thesecond data line.
 19. The system as claimed in claim 18, furthercomprising an electronic device, comprising: the display panel; and aninput unit, receiving image information and transporting the receivedimage information to the display panel.
 20. The system as claimed inclaim 19, wherein the electronic device is a cell phone, a digitalcamera, a personal computer assistant, a notebook, a desktop, atelevision, a car display, or a portable DVD player.